绗缝封装
绗缝封装(Quilt Packaging,QP)是一种集成电路封装和芯片间互连的封装技术,利用从微芯片边缘水平延伸的“结节”结构来。 [1][2]QP使用集成电路侧面突出的导电结节提高速度、降低功耗,实现封装内或多芯片模块上的多个芯片连接在一起,电气和机械上坚固的芯片间互连。绗缝封装由电气工程教授加里·伯恩斯坦(Gary H. Bernstein)领导的圣母大学研究人员团队发明。[3]
![](http://upload.wikimedia.org/wikipedia/commons/thumb/b/b9/Concept_Image_of_Quilt_Packaging_Nodules_and_RDL_Metal.jpg/220px-Concept_Image_of_Quilt_Packaging_Nodules_and_RDL_Metal.jpg)
![](http://upload.wikimedia.org/wikipedia/commons/thumb/6/6f/Quilt_Packaging_Nodules_with_Reflowed_Solder.jpg/220px-Quilt_Packaging_Nodules_with_Reflowed_Solder.jpg)
绗缝封装结节使用标准后道半导体器件制造技术创建,作为微芯片的组成部分,将焊料电镀在结节顶部,使芯片间实现亚微米精度互连。[4]
因此,绗缝封装技术可以在平面、2.5D和3D配置中集成具有不同技术或基板材料的多个芯片。 [5]这些结核结构可以用作极宽带宽、低损耗的电气I/O,实现亚微米级的机械芯片间对齐,并提供小至5微米的芯片间隙。[6]QP可以在各种衬底中实现,包括硅、砷化镓、碳化硅、氮化镓等,制成的小型高产“芯粒”可以“绗缝”在一起,创建更大的多功能元芯片。 [7]
特点
编辑与一级芯片封装的间接连接相比,QP是一种直接的芯片间互连,即“超级连接”,通过绗缝封装连接在一起裸晶结节直接从芯片侧面延伸出来。使用适当的对准夹具,将芯片推在一起并粘合,形成信号路径,在芯片之间传输多达数千个高速信号。在QP 中,芯片透过从芯片边缘水平突出的金属结节来连接,以创建超级连接。接合可以通过超声波焊接、激光焊接或锡焊来实现。 结节的对准可以通过外部夹具来执行,或者通过自对准结节和芯片结构的其他方法来执行,从而减轻一些精度要求。 最终的绗缝可以安装在一个包中或安装在MCM上。 这种方法仍然允许使用传统的凸块键合和引线键合,并且实际上对于允许从外部系统到成品绗缝的通信是必要的。[8][9]
射频模拟性能
编辑已在具有同质和异质半导体材料组的绗缝芯片组上进行了QP互连的多次测量插入损耗。射频S参数测量范围为DC至220 MHz。介于硅和砷化镓之间,已证明从DC到100 GHz,QP互连小于0.1 dB的插入损耗,[2]且高达220 GHz下有小于0.8 dB的插入损耗。[10]
数字性能
编辑绗缝封装互连已实现12吉比特/秒(Gbps)的比特率吞吐量,且在10 μm结节和10 μm芯片边缘的间距无失真。 [11]
光学/光子学
编辑初步的光耦合损耗模拟和测量表明芯片间耦合损耗<6 dB间隙小于4 μm。当间隙接近零时,损耗迅速改善,这可以通过绗缝封装装配公差来实现。 [12] [13]
参考
编辑- ^ Zheng, Quanling; Kopp, David; Khan, Mohammad Ashraf; Fay, Patrick; Kriman, Alfred M.; Bernstein, Gary H. Investigation of Quilt Packaging Interchip Interconnect With Solder Paste. IEEE Transactions on Components, Packaging and Manufacturing Technology. March 2014, 4 (3): 400–407. ISSN 2156-3950. S2CID 36676516. doi:10.1109/tcpmt.2014.2301738.
- ^ 2.0 2.1 Ashraf Khan, M.; Zheng, Quanling; Kopp, David; Buckhanan, Wayne; Kulick, Jason M.; Fay, Patrick; Kriman, Alfred M.; Bernstein, Gary H. Thermal Cycling Study of Quilt Packaging. Journal of Electronic Packaging. 2015-06-01, 137 (2). ISSN 1043-7398. doi:10.1115/1.4029245.
- ^ Gilroy, William G. Notre Dame researchers introduce “Quilt Packaging” to address interchip interconnect problem. Notre Dame News. 2006-10-09 [2024-01-26]. (原始内容存档于2024-01-26) (英语).
- ^ Ahmed, Tahsin; Butler, Thomas; Khan, Aamir A.; Kulick, Jason M.; Bernstein, Gary H.; Hoffman, Anthony J.; Howard, Scott S. FDTD modeling of chip-to-chip waveguide coupling via optical quilt packaging. Optical System Alignment, Tolerancing, and Verification VII (SPIE). 2013-09-10, 8844: 88440C. Bibcode:2013SPIE.8844E..0CA. S2CID 120463545. doi:10.1117/12.2024088.
- ^ Sparkman, Kevin; LaVeigne, Joe; McHugh, Steve; Kulick, Jason; Lannon, John; Goodwin, Scott. Scalable emitter array development for infrared scene projector systems. Infrared Imaging Systems: Design, Analysis, Modeling, and Testing XXV (SPIE). 2014-05-29, 9071: 90711I. Bibcode:2014SPIE.9071E..1IS. S2CID 53508849. doi:10.1117/12.2054360.
- ^ Quilt Packaging Concept | Indiana Integrated Circuits. [2024-01-26]. (原始内容存档于2024-01-26) (美国英语).
- ^ Khan, M. Ashraf; Kulick, Jason M.; Kriman, Alfred M.; Bernstein, Gary H. Design and Robustness of Quilt Packaging Superconnect. International Symposium on Microelectronics. January 2012, 2012 (1): 000524–000530. ISSN 2380-4505. doi:10.4071/isom-2012-poster_khan.
- ^ Bernstein, G.H.; Qing Liu; Zhuowen Sun; Fay, P. Quilt Packaging: A New Paradigm for Interchip Communication 1. IEEE. 2005 [2024-01-26]. ISBN 978-0-7803-9578-7. doi:10.1109/EPTC.2005.1614357. (原始内容存档于2018-06-19).
- ^ Ashraf Khan, M.; Zheng, Quanling; Kopp, David; Buckhanan, Wayne; Kulick, Jason M.; Fay, Patrick; Kriman, Alfred M.; Bernstein, Gary H. Thermal Cycling Study of Quilt Packaging. Journal of Electronic Packaging. 2015-06-01, 137 (2). ISSN 1043-7398. doi:10.1115/1.4029245.
- ^ Fay, Patrick; Bernstein, Gary H.; Lu, Tian; Kulick, Jason M. Ultra-wide Bandwidth Inter-Chip Interconnects for Heterogeneous Millimeter-Wave and THz Circuits. Journal of Infrared, Millimeter, and Terahertz Waves. 2016-04-29, 37 (9): 874–880. Bibcode:2016JIMTW..37..874F. ISSN 1866-6892. doi:10.1007/s10762-016-0278-5 .
- ^ Lu, Tian; Ortega, Carlos; Kulick, Jason; Bernstein, G. H.; Ardisson, Scott; Engelhardt, Rob. Rapid SoC prototyping utilizing quilt packaging technology for modular functional IC partitioning. New York, New York, USA: ACM Press. 2016: 79–85. ISBN 978-1-4503-4535-4. doi:10.1145/2990299.2990313.
- ^ Ahmed, Tahsin; Khan, Aamir A.; Vigil, Genevieve; Kulick, Jason M.; Bernstein, Gary H.; Hoffman, Anthony J.; Howard, Scott S. Optical Quilt Packaging: A New Chip-to-Chip Optical Coupling and Alignment Process for Modular Sensors. Cleo: 2014 (Washington, D.C.: OSA). 2014: JTu4A.56. ISBN 978-1-55752-999-2. S2CID 14432676. doi:10.1364/cleo_at.2014.jtu4a.56.
- ^ Ahmed, Tahsin; Lu, Tian; Butler, Thomas P.; Kulick, Jason M.; Bernstein, Gary H.; Hoffman, Anthony J.; Hall, Douglas C.; Howard, Scott S. Mid-Infrared Waveguide Array Inter-Chip Coupling Using Optical Quilt Packaging. IEEE Photonics Technology Letters. 2017-05-01, 29 (9): 755–758. Bibcode:2017IPTL...29..755A. ISSN 1041-1135. S2CID 7455544. doi:10.1109/lpt.2017.2684091.