内存级并行

内存级并行（英语：Memory-level parallelism，缩写为 MLP'），并行计算技术的一种，是计算机体系结构的一种，能够同时进行数个存储器操作，特别是在缓存未命中（cache miss），或转译后备缓冲器未命中（TLB miss）时。

在宏内核处理器架构下，内存级并行可以被视为是一种特殊的指令层级平行（ILP）。它也经常在超标量架构下出现。

相关条目

• 指令层级平行

参考文献

• "Enhancing memory level parallelism via recovery-free value prediction." H. Zhou and T. M. Conte. Proceedings of the 17th Annual International Conference on Supercomputing, ICS 2003.
• "A Case for MLP-Aware Cache Replacement", Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu, Yale N. Patt. Proceedings of the 33rd annual International Symposium on Computer Architecture (ISCA), 2006.
• "MLP-Aware Runahead Threads în a Simultaneous Multithreading Processor"(paper). Craeynest, K. Van, S. Eyerman, L. Eeckhout. Proc. of The 4th HiPEAC Int. Conf., Paphos, Cyprus, January 2009.
• "Microarchitecture optimizations for exploiting memory-level parallelism", Yuan Chou, B. Fahs, and S. Abraham, Computer Architecture, 2004. Proceedings. 31st Annual International Symposium on 2004.
• "Coming challenges in microarchitecture and architecture", Ronen, R.; Mendelson, A.; Lai, K.; Shih-Lien Lu; Pollack, F.; Shen, J.P. Proceedings of the IEEE Volume: 89 Issue: 3 Mar 2001
• "MLP yes! ILP no!" (abstract （页面存档备份，存于互联网档案馆） / slides （页面存档备份，存于互联网档案馆）), A. Glew. In Wild and Crazy Ideas Session, 8th International Conference on Architectural Support for Programming Languages and Operating Systems, October 1998.