設計自動化標準委員會

設計自動化標準委員會（英語：Design Automation Standards Committee, DASC）是由IEEE中對設計自動化感興趣的人結成的子學會、IEEE計算機社團（Computer Society）和IEEE標準協會（IEEE Standards Association）共同組成。該組織負責監管有關計算機輔助設計（即設計自動化）的IEEE標準。它也是IEEE計算機社團的一部分

設計自動化委員會贊助的標準包括：

• IEEE 1076 Standard VHDL Language Reference Manual (VASG)[1]（頁面存檔備份，存於互聯網檔案館）
  • VHDL-200x [2]（頁面存檔備份，存於互聯網檔案館）: the next revision
  • Issues Screening and Analysis Committee (ISAC) [3]（頁面存檔備份，存於互聯網檔案館）
  • VHDL Programming Language Interface Task Force (VHPI) [4]（頁面存檔備份，存於互聯網檔案館）
  • P1076.1 Standard VHDL Analog and Mixed-Signal Extensions (VHDL-AMS)
  • P1076.1.1 Standard VHDL Analog and Mixed-Signal Extensions - Packages for Multiple Energy Domain Support (StdPkgs)
  • P1076.4 Standard VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification (VITAL)
  • P1076.6 Standard for VHDL Register Transfer Level (RTL) Synthesis (SIWG)
• P1364.1 Standard for Verilog Register Transfer Level Synthesis (VLOG-Synth)
• P1481 Standard for Integrated Circuit (IC) Open Library Architecture (OLA) (IEEE1481R)
• P1499 Standard Interface for Hardware Description Models of Electronic Components (OMF)
• P1603 Standard for an Advanced Library Format (ALF) Describing Integrated Circuit (IC) Technology, Cells, and Blocks (ALF)
• P1647 Standard for the Functional Verification Language 'e' (eWG)
• P1666 Standard SystemC Language Reference Manual [cosponsored with IEEE-SA CAG]
• P1685 SPIRIT XML Standard for IP Description (IEEE-1685)
• P1735 (Study Group)
• SystemVerilog Working Group
  • P1800 SystemVerilog: Unified Hardware Design, Specification and Verification Language (SV-IEEE1800) [cosponsored with IEEE-SA CAG]
  • P1364 Standard for Verilog Hardware Description Language (IEEEVerilog)
• IEEE 1801 Standard for the Design and Verification of Low Power Integrated Circuits, the Unified Power Format
• IEEE 1850 Standard for PSL: Property Specification Language (cosponsored with IEEE-SA CAG)